1. Field of the Invention
This invention relates to digital computers and specifically to the architecture and methodology used in fabricating digital computers.
2. Description of the Prior Art
Computer architecture since the inception of the digital computer has undergone relatively few basic changes. Most computers comprise a large memory, an arithmetic logic unit (ALU) and an input/output (I/O) section. The computer functions by considering the memory as a single unit. The memory can be any size within the addressing capabilities of the ALU, but it is a single unit in a block diagram point of view. When an external event occurs the input/output module "interrupts" the ALU and forces the ALU to store its state at the time of the interrupt and to subsequently service that interrupt. After ascertaining the "where" and "what" of the interrupt, appropriate sub-routines are called from memory to service the interrupt. The decision must be made and the appropriate memory fetches must be executed. At the conclusion of the interrupt the ALU returns to its previous state and continues on with its internal computation.
A more advanced computer architecture utilizes the same three modules with the I/O still interrupting the memory. Here the ALU further has enhanced capability by means of "stunt boxes" and an onboard cache memory. This onboard cache memory allows the execution of small sub-routines directly on the ALU without having to use the slower bus structure connecting the three basic modules.
The memory in such an advanced computer has several ports, only one of which may be used at a single time. In order for the I/O to communicate with the memory it is necessary that the same bus be utilized that interconnects the memory with the ALU. However, for getting high speed data into memory a direct memory access (DMA) is used. This DMA is executed by interrupting the ALU and subsequently shutting down the basic bus which interconnects the ALU with the memory and the I/O and transferring bus control to the DMA channel and executing the data transfer from a disk or other associated external device. Thus, in this type of prior art advanced computer architecture the DMA I/O ports access the memory using the bus interconnecting the memory with the CPU. The DMA however is able to communicate with the memory without using the CPU. This generally brings about the common misconception that I/O and the CPU run independendly of each other. This however is not the case, for in a conventional DMA scheme transfers to and from memory occur during the execute cycle of the CPU. This works well as long as the total time required by the DMA's I/O is less than the execute time available. When this rate is exceeded either the CPU performance degrades rapidly or the DMA cannot take the I/O. Either occurrence usually has disastrous results.
Furthermore, prior art computer architecture when handling serial I/O devices such as terminals usually requires the interpretation of each character as received and often a response character. In a conventional architecture this is done by interrupting the CPU after each character. The CPU requires many CPU cycles to store away its current state, interpret the character and then to restore its previous state. This limits the number of simultaneous serial I/O channels that can be handled by the CPU. For example, if it takes a CPU one hundred microseconds to handle a character, this limits the system to ten 9,600 baud ports. To handle more ports it is necessary to add external processors to handle the handshaking. This makes the system more complex and expensive.
Thus the basic computer architecture bus is limited and single minded. It can only do one thing at a time and must do it over the memory port bus. In order to make the computer run faster, it is necessary to make the speed of execution of a single instruction faster. The classical architecture is thus analogous to a supersonic jet making more and more trips across the Atlantic as opposed to the "air bus" which is the analogous equivalent to the present invention as disclosed herein.
It has also been found difficult for prior art computer architectures to function as multi-processors. Multiprocessors by virture of the inherent architecture used to data cannot significantly enhance computer capability since, in effect, transfer between shared memories means that one CPU is shut down while the other does a memory access transfer. Common data base is of course important, but the rate of execution of a program is not substantially enhanced using such a multi-processor approach.
In the present invention the solution to the problem of greater computational speed by a digital computer is accomplished by a totally new approach by utilizing a basic change in digital computer architecture. The present invention is a digital computer that uses partitioned memory, which is always available to external events, independent of internal arithmetic logic unit requirements. The central processor or arithmetic logic unit continues to run at a given rate, yet, for most computational requirements is never stopped with respect to external events. To achieve this result the memory and the I/O are combined into a single intelligent module with the memory structure utilizing multi-synchronous ports. The central processing unit (CPU) thus communicates with the composite intelligent memory and input/output module (MIO) during one phase of a three phase clock cycle, while the other two phases of the clock cycle enable the MIO to communicate with external devices. Thus, unlike the prior art computer architecture, the amount of data transferred between the memory and the external devices can never adversely affect the computational abilities of the CPU since access to the memory by the CPU can never be impeded by data transfer to and from external devices.
Furthermore, the present invention, by use of interprocessor modules (IPB), which may be software modified MIO's, allows the addition of any number of additional CPU's with their own associated MIO's and IPB's. The IPB with its associated memory allows two interconnected CPU's to communicate with each other through the use of shared memory. However, since the IPB, like the MIO, utilizes the same three phase timing cycles, interference between communicating CPU's is prevented. A cascade arrangement of CPU's with associated MIO's is achievable by the present invention. Thus a multi-processor digital computer is realizable in a simple and straightforward way.